Session
Technical Session XII: Software
Abstract
Autonomous dynamic event scheduling using Iterative Repair techniques is an essential component of successful space missions, as it enables spacecraft to adaptively schedule tasks in a dynamic, real-time environment. Event rescheduling is a compute-intensive process. Typical applications involve scheduling hundreds of events that share tens or hundreds of resources. We are developing a set of tools for automating the derivation of application-specific processors (ASIPs) from ANSI C source code that perform this scheduling in an efficient manner. The tools will produce VHDL code targeted for a Xilinx Virtex 4 FPGA (Field Programmable Gate Array). Features of FPGAs, including large processing bandwidth and embedded ASICs and block RAMs, are exploited to optimize the design. Iterative Repair problems are generally solved using Simulated Annealing, which works by gradually improving an initial solution over thousands of iterations. We propose an FPGA-based architectural framework derived from ANSI C function-level blocks for accelerating these computations by optimizing the process of (1) generating a new solution, (2) evaluating the solution, and (3) determining whether the new solution should be accepted. Each step is implemented in VHDL through data- and control-flow analysis of the source C code. We discuss an architecture template for automated processor design.
Presentation Slides
Deriving FPGA Based Custom Soft-Core Microprocessors for Mission Planning Algorithms
Autonomous dynamic event scheduling using Iterative Repair techniques is an essential component of successful space missions, as it enables spacecraft to adaptively schedule tasks in a dynamic, real-time environment. Event rescheduling is a compute-intensive process. Typical applications involve scheduling hundreds of events that share tens or hundreds of resources. We are developing a set of tools for automating the derivation of application-specific processors (ASIPs) from ANSI C source code that perform this scheduling in an efficient manner. The tools will produce VHDL code targeted for a Xilinx Virtex 4 FPGA (Field Programmable Gate Array). Features of FPGAs, including large processing bandwidth and embedded ASICs and block RAMs, are exploited to optimize the design. Iterative Repair problems are generally solved using Simulated Annealing, which works by gradually improving an initial solution over thousands of iterations. We propose an FPGA-based architectural framework derived from ANSI C function-level blocks for accelerating these computations by optimizing the process of (1) generating a new solution, (2) evaluating the solution, and (3) determining whether the new solution should be accepted. Each step is implemented in VHDL through data- and control-flow analysis of the source C code. We discuss an architecture template for automated processor design.
