Session
Technical Session IX: Mission Enabling Technologies I
Abstract
The Mini-PnP 3x3 mm ASIC has been designed with Radiation Hardened by Design (RHBD) techniques using the IBM9LP CMOS process. The chip includes a high performance 8 bit PIC based RISC with 4Kx14 EDAC protected on chip Instruction RAM and two banks of registers supporting 192 bytes each. The registers are implemented using temporal latch technology and are SEU immune. The architecture supports two master inter-integrated circuit (I2C) buses where one can be configured as an I2C slave. The chip implements a SPI Master core. The cores are integrated with the RISC processor using a Wishbone Bus Crossbar switch. Mini-PnP ASIC supports bootup from an external SPI based Non Volatile Memory (NVM). The reading of the “eXtensible Transducer Electronic Datasheet” (xTEDS) from the external SPI NVM is also supported for Plug and Play applications. The ASIC Mini- PnP Silicon has been successfully tested with the design clock of 50 MHz. In this paper, the power consumption of the core power versus clock scaling is presented. The goal of the multi-chip module (MCM) implementation of Mini-PnP is to reduce the system size to around 15x15mm with integrated ASIC Mini-PnP, I2C driver circuits, SPI NVM (128Kbytes), and multiplexing to support external programming of the SPI NVM. A Chip on Board (COB) solution will be presented.
Presentation Slides
Radiation Hardened by Design 8 bit RISC with Dual I2C Bus Support and SPI for External NVM Support
The Mini-PnP 3x3 mm ASIC has been designed with Radiation Hardened by Design (RHBD) techniques using the IBM9LP CMOS process. The chip includes a high performance 8 bit PIC based RISC with 4Kx14 EDAC protected on chip Instruction RAM and two banks of registers supporting 192 bytes each. The registers are implemented using temporal latch technology and are SEU immune. The architecture supports two master inter-integrated circuit (I2C) buses where one can be configured as an I2C slave. The chip implements a SPI Master core. The cores are integrated with the RISC processor using a Wishbone Bus Crossbar switch. Mini-PnP ASIC supports bootup from an external SPI based Non Volatile Memory (NVM). The reading of the “eXtensible Transducer Electronic Datasheet” (xTEDS) from the external SPI NVM is also supported for Plug and Play applications. The ASIC Mini- PnP Silicon has been successfully tested with the design clock of 50 MHz. In this paper, the power consumption of the core power versus clock scaling is presented. The goal of the multi-chip module (MCM) implementation of Mini-PnP is to reduce the system size to around 15x15mm with integrated ASIC Mini-PnP, I2C driver circuits, SPI NVM (128Kbytes), and multiplexing to support external programming of the SPI NVM. A Chip on Board (COB) solution will be presented.
