Radiation Hardened Very Low Power ASICs for Satellite Command Control and Data Handling (C&DH) and Sensor Integration

Radiation Hardened Very Low Power ASICs for Satellite Command Control and Data Handling (C&DH) and Sensor Integration

To enable missions in harsh radiation environments and for long term missions, we have developed a family of low power radiation hardened ASICs on the IBM 90nm CMOS 9LP Process. The chips include System on a Chip (SoC) designs ranging from the 32 bit OpenRISC, the 8 bit 8051XC and an 8-bit RISC architecture. For two SoCs (8 bit and 32 bit) we have incorporated two OpenCores 16550 compatible UARTs in addition to six 32 bit OpenCores Pulse Width Modulation and Timers (PTCs). The PTC’s can be used for Servo Motor Control, Timing events, and clock sources. All SoC’s support a dedicated SPI Slave for firmware download as well as a SPI Master for firmware boot up from external SPI Non Volatile Memory (NVM). A SPI Slave to Parallel Non-Volatile Memory (NVM) ASIC has been developed that converts Parallel NVM to a SPI Slave interface. This allows for both boot up from external Parallel NVM and programming external Parallel NVM up to 16MBytes. The SoC’s all run at 50MHz clock rates. All sequential logic is implemented with Temporal Latch ® technology which makes the designs SEU immune up to 60 LET. The chips are TID hard to 1 MRad.