All 2015 Content
Session
Technical Session VI: Ground Systems and Communications
Abstract
Software Defined Radios (SDRs) have emerged as a viable approach for space communications over the last decade by delivering low-cost hardware and flexible software solutions. The flexibility introduced by the SDR concept not only allows the realization of multiple standards on one platform, but also promises to ease the implementation of one communication standard on differing SDR platforms by waveform porting. This technology would facilitate implementing reconfigurable nodes for parallel satellite reception in Mobile/Deployable Ground Segments. The SDR architecture was implemented initially in C/C++ and tested over varied embedded platforms and at different data rates from 1.2 to 19.2 kbps. Profiling using gprof demonstrated the need to move the up and down sampling blocks demanding higher computation to Field Programmable Gate Array (FPGA) logic in order to benefit new architecture optimization and thereby facilitating more than one signal at any given time. The paper includes the implementation of the Digital Down Converter (DDC) block in VHDL and design tradeoffs that yields insight into optimal solutions along with effective evaluation of the new candidate architecture.
Software Defined Radio (SDR) for Parallel Satellite Reception in Mobile/Deployable Ground Segments
Software Defined Radios (SDRs) have emerged as a viable approach for space communications over the last decade by delivering low-cost hardware and flexible software solutions. The flexibility introduced by the SDR concept not only allows the realization of multiple standards on one platform, but also promises to ease the implementation of one communication standard on differing SDR platforms by waveform porting. This technology would facilitate implementing reconfigurable nodes for parallel satellite reception in Mobile/Deployable Ground Segments. The SDR architecture was implemented initially in C/C++ and tested over varied embedded platforms and at different data rates from 1.2 to 19.2 kbps. Profiling using gprof demonstrated the need to move the up and down sampling blocks demanding higher computation to Field Programmable Gate Array (FPGA) logic in order to benefit new architecture optimization and thereby facilitating more than one signal at any given time. The paper includes the implementation of the Digital Down Converter (DDC) block in VHDL and design tradeoffs that yields insight into optimal solutions along with effective evaluation of the new candidate architecture.
