Session
Session 12: Advanced Technologies 3
Abstract
As small satellites continue to proof capable of producing useful scientific data and supporting commercial applications their typical safe orbit/short life span missions are replaced by longer duration missions at harsher orbits. Radiation effects concerns become more serious and steps need to be taken toward improving the reliability of the spacecraft’s electronics. Thus, there is a need for high reliability computing engines capable of surviving this new type of mission. The use of qualified radiation hardened parts is generally too expensive for this new type of missions. Less expensive alternatives have focused on designing computing engines using radiation effects mitigation approaches at the architectural level (e.g redundancy, testing, failsafe mechanisms, etc). IDEAS-TEK has taken the approach of designing a custom radiation hardened ASIC using the same techniques that high-end radiation hardened microelectronics is designed with, with the exception of high end costly tools and processes. This paper presents SHARP- a 32-bit RISC processor being developed under sponsorship of AFRL as a radiation hardened ASIC at 180nm technology node. SHARP prototypes (ASICs and equivalent soft-cores FPGA implementations) are expected to be available early 2018.
Presentation
SHARP: A Space HARdened Procesor for Next Generation CubeSats
As small satellites continue to proof capable of producing useful scientific data and supporting commercial applications their typical safe orbit/short life span missions are replaced by longer duration missions at harsher orbits. Radiation effects concerns become more serious and steps need to be taken toward improving the reliability of the spacecraft’s electronics. Thus, there is a need for high reliability computing engines capable of surviving this new type of mission. The use of qualified radiation hardened parts is generally too expensive for this new type of missions. Less expensive alternatives have focused on designing computing engines using radiation effects mitigation approaches at the architectural level (e.g redundancy, testing, failsafe mechanisms, etc). IDEAS-TEK has taken the approach of designing a custom radiation hardened ASIC using the same techniques that high-end radiation hardened microelectronics is designed with, with the exception of high end costly tools and processes. This paper presents SHARP- a 32-bit RISC processor being developed under sponsorship of AFRL as a radiation hardened ASIC at 180nm technology node. SHARP prototypes (ASICs and equivalent soft-cores FPGA implementations) are expected to be available early 2018.
