Session
Weekday Poster Session 1
Location
Utah State University, Logan, UT
Abstract
A common architecture for COTS payload computers in space applications combines a COTS APU (CPU+GPU combo) with an FPGA. The FPGA provides monitoring, Triple Modular Redundancy (TMR), and other space-suitable properties, while the APU serves as the high-performance compute component. The FPGA can also be utilized for custom interfaces and tasks it excels at, such as certain real-time operations.
Efficient Data Pipelines for Combined FPGA/APU Systems
Utah State University, Logan, UT
A common architecture for COTS payload computers in space applications combines a COTS APU (CPU+GPU combo) with an FPGA. The FPGA provides monitoring, Triple Modular Redundancy (TMR), and other space-suitable properties, while the APU serves as the high-performance compute component. The FPGA can also be utilized for custom interfaces and tasks it excels at, such as certain real-time operations.
