Session
Poster Session 3
Location
Salt Palace Convention Center, Salt Lake City, UT
Abstract
Multi-phase power is important to design highly efficient solutions for next-generation space avionics systems, but noise, current sharing accuracy and beat pulses can all contribute to the complexity of a power system's design. The latest FPGAs and ACAPs have very specific DC and AC regulation tolerances, so it can be difficult to manage power while considering size, efficiency, reliability and cost.
This poster will demonstrate methods to scale and manage multi-phase power systems through the inclusion of power management-specific clock distribution ICs and show how they can be used to implement a variety of solutions that balance efficiency and accuracy with size and cost.
While efficient multi-phase power can absolutely be achieved without any additional clock distribution ICs, precise control over phase delay and frequency division can reduce ripple and noise, resulting in significantly more accurate current sharing. Therefore, the overall solution size can be minimized through a reduction in input and output capacitance while meeting stringent regulation tolerance requirements.
Document Type
Event
Techniques for Optimizing SWaP-C Through Multi-Phase Clock Distribution
Salt Palace Convention Center, Salt Lake City, UT
Multi-phase power is important to design highly efficient solutions for next-generation space avionics systems, but noise, current sharing accuracy and beat pulses can all contribute to the complexity of a power system's design. The latest FPGAs and ACAPs have very specific DC and AC regulation tolerances, so it can be difficult to manage power while considering size, efficiency, reliability and cost.
This poster will demonstrate methods to scale and manage multi-phase power systems through the inclusion of power management-specific clock distribution ICs and show how they can be used to implement a variety of solutions that balance efficiency and accuracy with size and cost.
While efficient multi-phase power can absolutely be achieved without any additional clock distribution ICs, precise control over phase delay and frequency division can reduce ripple and noise, resulting in significantly more accurate current sharing. Therefore, the overall solution size can be minimized through a reduction in input and output capacitance while meeting stringent regulation tolerance requirements.
