A Partial TMR Technique for Improving Reliability at a Low Hardware Cost in FPGAs

Salt Lake Community College

The flexibility combined with the computational capabilities of FPGAs make them a very attractive solution for space-based computing platforms. However, SRAM-based FPGAs are susceptible to radiation effects, including Single Event Upsets. In order to increase the fault tolerance of FPGA designs, fault mitigation techniques, such as Triple Module Redundancy, can be applied. Such techniques, however, can be excessive in terms of hardware costs. This work investigates the tradeoffs between fault mitigation techniques for FPGA designs and the corresponding costs of such mitigation. A particular focus is placed upon identifying design components that serve to benefit most from the application of fault tolerance techniques, and investigating the tradeoffs associated with applying mitigation to these most sensitive design sections.