Location
Room # EB204
Start Date
5-6-2019 11:20 AM
Description
This paper presents a successive approximation analog-to-digital converter (SAR ADC) design, which operates with a 0.2 V power supply. The design utilizes a dynamic bulk biasing scheme to dynamically adjust the relative NMOS and PMOS strengths, which are very sensitive to temperature, process, and mismatch variations at low supply voltages. The design achieves a very low power consumption due to the 0.2 V supply. Several circuits in the design are optimized for full functionality at 0.2 V. Extracted simulations show a total power consumption of 9 nW with a peak SNDR of 61.3 dB and a Walden Figure of Merit of 1.91 fJ/conversion-step.
A 10-bit SAR ADC with an Ultra-Low Power Supply
Room # EB204
This paper presents a successive approximation analog-to-digital converter (SAR ADC) design, which operates with a 0.2 V power supply. The design utilizes a dynamic bulk biasing scheme to dynamically adjust the relative NMOS and PMOS strengths, which are very sensitive to temperature, process, and mismatch variations at low supply voltages. The design achieves a very low power consumption due to the 0.2 V supply. Several circuits in the design are optimized for full functionality at 0.2 V. Extracted simulations show a total power consumption of 9 nW with a peak SNDR of 61.3 dB and a Walden Figure of Merit of 1.91 fJ/conversion-step.
Comments
Session 6