Location
Orbital ATK Conference Center
Start Date
5-7-2018 11:45 AM
Description
A 0.2V 10-bit 5 kS/s Successive Approximation Register ADC design is presented. This design achieves a very low power consumption due to the ultra-low power supply voltage used. Different aspects in the ADC design are optimized for 0.2V and modified to meet the speed requirements for the ADC. Preliminary Cadence simulations show a 4nW total power consumption with a peak SNDR of 57 dB and a FOM of 1.3 fJ/conversion-step.
A 10b SAR ADC with an Ultra-Low Power Supply
Orbital ATK Conference Center
A 0.2V 10-bit 5 kS/s Successive Approximation Register ADC design is presented. This design achieves a very low power consumption due to the ultra-low power supply voltage used. Different aspects in the ADC design are optimized for 0.2V and modified to meet the speed requirements for the ADC. Preliminary Cadence simulations show a 4nW total power consumption with a peak SNDR of 57 dB and a FOM of 1.3 fJ/conversion-step.
Comments
Session 4